A Phase-Locked Loop (PLL) is a control system capable of generating an output signal having a phase related to the phase of an input reference signal. PLLs are widely used in communication systems, for example to process clock signals. Depending on the application, a PLL can be implemented in a number of different ways, including fully-analog implementations, fully-digital implementations, software implementations and a mix thereof. Two or more PLLs may be coupled together in implementations for various applications.
A PLL can be configured as a frequency synthesizer that functions to generate a signal with a desired frequency based on a given reference frequency by using a frequency divider in the feedback loop. A fractional-N PLL, in contrast to an integer-N PLL, comprises a fractional divider and may have a frequency conversion factor, e.g., the divide ratio, N being a non-integer.
Typically, a fractional-N PLL frequency synthesizer comprises a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a fractional divider in the feedback loop. The VCO outputs a signal having a frequency that is N times the frequency of a reference signal. The fractional divider divides the output signal by N and generates a feedback signal. The phase frequency detector compares the phase of the reference and the feedback signal, and accordingly outputs an error signal to the loop filter, which is usually a low-pass filter, that sets the loop dynamics, such as bandwidth, damping, and setting time. The loop filter outputs a voltage to the VCO based on the error signal to adjust the frequency of the VCO output. Conventionally, the divide ratio N remains static during the foregoing process.
Unfortunately, an input signal to a PLL often contains a significant amount of undesired phase noises or jitters, primarily coming from analog function blocks in the circuit, which tend to be passed to the output signal via the PLL frequency synthesizer. This causes synchronization issues. The low-bandwidth nature of a conventional jitter attenuator, compounded with relatively low jitter transmit clock frequencies, has made implementation difficult. For example, an analog PLL addressing the jitter performance issue would require complex circuitry and silicon area to enable low bandwidth, which increases cost. A digital PLL addressing this issue would require implementing challenging design linearity specification for a digital control oscillator.